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Freescale Semiconductor Advance Information
Document Number: MC33784 Rev 3.0, 11/2009
DSI 2.02 Sensor Interface
The 33784 is a slave, Distributed System Interface Bus (DBUS), version 2.02 compatible device, optimized as a sensor interface. The device contains circuits to power sensors such as accelerometers, and to digitize the analog level from the sensor. The device is controlled by commands over the bus, and returns measured data and other information over the bus. Features * * * * * * * DSI version 2.02 compatible 2-channel, 10-bit analog-to-digital converter (ADC) 3 pins configurable as logic inputs or outputs Provides regulated +5.0v output for sensor power from bus On-board clock (no external elements required) Includes bus switches on bus and bus return Pb-free packaging designated by suffix code EF
33784
SENSOR INTERFACE
EF SUFFIX (PB-FREE) 98ASB42566B 16-LEAD SOICN
ORDERING INFORMATION
Device MCZ33784EF/R2 Temperature Range (TA) - 40C to 125C Package 16 SOICN
33781
BUS
33784
REGOUT RTNIN AGND AN0 AN1 I/O0 I/O1 I/O2 BUSOUT RTNOUT BUSIN H_CAP IDDQ TEST1 TOUT TEST2 VCC BUSIN RTNIN
33784
BUSOUT RTNOUT To other 33784 Slaves
XY ACCELEROMETER
AGND
Figure 1. 33784 Simplified Application Diagram (Daisy Chain Shown)
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2008 - 2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
H_CAP Rectifier BUSIN High Side Bus Switch 0-35 V Receiver Data Response Current 0-11mA 8.0mA/s Received Message from MCU Oscillator 10MHz DataOut <2.0> I/O Buffers DataOut <0> I/O0 I/O1 I/O2 TEST1 TEST2 MUX DataOut <2> SEL 10-Bit ADC POR IDDQ DataOut <1> 2.2F or 4.7F Typical
BUSOUT
Frame
Bandgap Reference
Bus Return
Logic Command Decode State Machine Response Generation Power Management 5.0V Regulator BG Reference Bias Currents
TOUT
REGOUT CRO = 2.2F AGND
AN0 AN1 RTNIN Low Side Bus Switch RTNOUT
Figure 2. 33784 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
REGOUT TEST2 I/O0 I/O1 I/O2 AN0 AGND AN1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
H_CAP BUSIN BUSOUT RTNIN RTNOUT TOUT IDDQ TEST1
Figure 3. 33784 Pin Connections Table 1. 33784 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number 1 2 3 4 5 6, 8 7 9 10 11 12 13 14 15 16 Pin Name REGOUT TEST2 I/O0 I/O1 I/O2 AN0,AN1 AGND TEST1 IDDQ TOUT RTNOUT RTNIN BUSOUT BUSIN H_CAP Pin Function Output Test Input/Output Formal Name Regulator Output Test2 Logic I/O Definition Pin provides a regulated 5.0V output. The power is derived from the bus. This pin must be grounded in the application. Pins can be used to provide a logic level output or a logic input.
Input Ground Reference Test Test Test Power Power Output Input Output
Analog Input Analog Ground Test1 IDDQ Test Output Bus Return Bus Return DBUS Output DBUS Input Holding Capacitor
Inputs to the ADC. Pin is the low reference level and power return for the analog-to-digital converter (ADC). It is internally connected to RTNIN. This pin must be grounded in the application. Input pin for measuring device quiescent current. Must be left open in the application. This pin must be grounded in the application. Switched RTNIN pin, attaches to the next RTNIN pin in the daisy chain. Pin attaches to the low side of the differential bus, and provides the common return for power and signalling. It is internally connected to AGND. Switched BUSIN Pin, attaches to the next BUSIN pin in the daisy chain. Pin attaches to the high side of the differential bus and responds to initialization commands. A capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the REGOUT pin during non-idle periods.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to Analog Ground (AGND) unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS I /O0, I/O1, I/O2, AN0, AN1, TEST1, TEST2, TOUT Voltage I /On, ANn, TESTn, TOUT Pin Current BUSOUT Voltage, BUS SW = open BUSIN Voltage, BUS SW = open RTNOUT Voltage, BUS SW = open H_CAP Voltage BUSIN, BUSOUT, and H_CAP Current (Continuous) BUSIN, RTNIN, reverse current (max 5 ms) RTNIN, RTNOUT Current IDDQ Voltage VREG Range ESD Voltage(1) Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Corner pins All other pins THERMAL RATINGS Storage Temperature Operating Ambient Temperature Operating Junction Temperature THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS Resistance, Junction-to-Ambient (Single Layer (1s) PCB Board) Resistance, Junction-to-Board (Multi-Layer (2s2P) PCB Board) Peak Package Reflow Temperature During Reflow ,
(2) (3)
Symbol
Value
Unit
VIO IIO VIN VIN VIN VIN IIN IREVLK IBUSRTN VIDDQ VRO VESD
-0.3 to VREGOUT + 0.3 5.0 -14 to 40 -0.3 to 40 -14 to 25 -0.3 to 40 400 400 400 2.75 0.3 - 7.0
V mA V V V V mA mA mA V V V
2000 200 750 500
TS TA TJ
-55 to 150 -40 to 125 -40 to 150
C C C
RJA RJB TPPRT
125 62 Note 3
C/W C/W C
Notes 1. ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500), ESD2 testing is performed in accordance with the Machine Model (MM) (CZAP = 200pF, RZAP = 0); and Charge Body Model (CBM) 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions -0.3V VBUSIN 30V, 6.0V VH_CAP 30V, - 40C TA 125C, RTNIN=AGND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Internal Quiescent Current Drain VH_CAP = 25V, I /O = Input BUSIN to H_CAP Rectifier Voltage Drop IHCAP = 15mA IHCAP = 100mA H_CAP Diode Efficiency
(4)
Symbol IQ
Min
Typ
Max
Unit mA
- VRECT - -
-
4.0 V
0.75 0.9
1.00 1.4 %
IHCAP = 400mA, BUSIN = 25V BUSIN Bias Current VBUSIN = 8.0V, VH_CAP = 9.0V VBUSIN = 4.5V, VH_CAP = 9.0V when device is not signalling Rectifier Leakage Current VBUSIN = 0V, VH_CAP = 25V REGOUT 5.8V < VH_CAP 25V, 0 IRO 14mA REGOUT Line Regulation IRO = 14mA, 6.0V VH CAP 25V IRO is the total internal and external load current REGOUT Load Regulation 0 IRO 14mA, 6.0V VH CAP 25V, REGOUT Transient Line Regulation(5) IRO = 14mA, 0 V VBUSIN 30 V, 8V/us @ BUSIN, or, 5V/us @ HCAP CRO = 2.2 uF, CRO ESR = 0.063-2.2 @ 20kHz, 0.004-0.072 @ 200kHz REGOUT Transient Load Regulation(5) 0 IRO 14mA, 6.0V VH CAP 25V, 2mA/us @ IRO, CRO = 2.2uF, CRO ESR = 0.063-2.2 @ 20kHz, 0.004-0.072 @ 200kHz REGOUT Current Limit, VREGOUT = 0V Hi-side Bus Switch Resistance 0 VBUSIN 30V, ISWH = 160mA (Bus Switch Active) Low-side Bus Switch Resistance ISWL = 160mA (Bus Switch Active) Notes 4. EFF = 400mA/IBUSIN - IQ 5. Assured by design. RSWL ILMT RSWH VRLD VRLINE VRO IRLKG IBIAS
99
-
- A
-100 -100 -20
-
100 100
-
20
A
4.9
5.0
5.1
V
-
-
20
mV
-
-
15
mV
-
-
(25)
mV
-
-
(50)
mV
25
35
45
mA
-
3.0
6.0
-
3.0
6.0
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -0.3V VBUSIN 30V, 6.0V VH_CAP 30V, - 40C TA 125C, RTNIN=AGND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Bus Switch Resistance Matching = | RSWH - RSWL |, TA = 25C = | RSWH - RSWL |, TA = 125C I/O0, I/O1, I / O2, and TEST Pull-down Current VIN = 1.0V I/O0, I/O1, I/O2, and TEST Leakage Current I/On, TEST = 0V AN0, AN1 Pull-down Current (Enabled mode) VIN = 1.0V(6) AN0, AN1 Leakage Current (Disabled mode)(6) BUSIN Logic Thresholds Signal Frame BUSIN Hysteresis Signal Frame BUSIN Response Current VBUSIN = 4.0V VBUSIN = 1.175V BUSIN, BUSOUT Leakage Current High Side Bus Switch Open BUSIN = 25V, BUSOUT = 0V BUSIN= 0V, BUSOUT = 16V RTNIN, RTNOUT Leakage Current Low Side Bus Switch Open RTNIN = 14V, RTNOUT = 0V RTNIN = 0V, RTNOUT = 16V RTNIN to BUSOUT Leakage Current High Side Bus Switch Open RTNIN = 14, BUSOUT 0V ADC Resolution ANn Input Capacitance(7) Input Source Impedance(7) ADC Code Conversion Error (INL) Source Resistance < 1.0k Full Scale Error 6. 7. ADCFS -3.5 - +3.5 LSB ADCRES CADC ZIN ADCINL 10 - - -3.5 10 - - - 10 20 5.0 +3.5 bit pF k LSB ICROSSLK -20 -125 -20 - - - 20 125 20 A IBUSRTNLK A IBUSINLK VHYSS VHYSF IRSP 9.9 7.0 -20 11 - - 12.1 - 20 A 60 100 - - 120 300 mA VTHS VTHF 2.8 5.5 3.0 6.0 3.2 6.5 mV IANnLKG -1.0 - 1.0 A V IPDANn 5.0 - 20 A ILK IPD 5.0 -10 - - 20 10 A Symbol RDSW - - 0.3 0.6 A Min Typ Max Unit
In the default, AN0 pull-down current is disabled and AN1 pull-down current is enabled. AN1 pull-down current is disabled during AN1 A2D conversion. At the same time, AN0 pull-down current is enabled. Assured by design.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -0.3V VBUSIN 30V, 6.0V VH_CAP 30V, - 40C TA 125C, RTNIN=AGND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Absolute Error(8) 0.5V < Input Voltage < 4.5V ADC Code Conversion Error (DNL) Source Resistance < 1.0 k I / O Input Levels Input High Voltage Input Low Voltage I/O Input Hysteresis(8) I / O Logic Output Levels Output Low (IL = 1.0mA) Output High (IL = -500A) POR Detect Thresholds Voltage at HCAP Voltage at REGOUT Notes 8. Assured by design. VPORHCAP VPORREG 6.0 4.25 6.39 4.5 6.77 4.75 VOL VOH 0 VREGOUT 0.8 - - 0.8 VREGOUT V VIH VIL VHYS 70%*VREG - 300 - - - 30%*VREG mV V V ADCDNL - - 2.0 LSB Symbol ADCABS Min -4.0 Typ - Max +4.0 Unit LSB
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions -0.3V VBUSIN or VBUSOUT 30V, 6.0V VH_CAP 30V, - 40C TA 125C, AGND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Internal Oscillator Frequency Internal Oscillator Duty Cycle Initialization to Bus Switches Close Communication Data Rate Loss of Signal Reset Time
(9)
Symbol fOSC DCOSC tBS DRATE tTO tADC t ITR_R t ITR_F tRSP_R
Min 9.0 45 - 100 2.0
Typ 10.0 50 - - -
Max 11.0 55 50 200 4.0
Unit MHz % s kbps ms s mA /s
Maximum Time for BUSIN to Be Below Frame Threshold ADC Code Conversion Time(10) BUSIN Response Current Slew Rate 1.0mA to 9.0mA Transition Rise 9.0mA to 1.0mA Transition Fall BUSIN Timing to Response Current BUSIN Negative Voltage Transition = 3.0V to IRSP = 7.0mA Rise TA = -40C TA = +25C TA =+125C BUSIN Negative Voltage Transition = 3.0V to IRSP = 5.0mA Fall Bus Signal Duty Cycle(9) Logic [0] (~ 1/3 + 20%) Logic [1] (~ 2/3 + 20%) I/O Transition Time (CLoad = 50pF)(9)
(9)
-
-
20
- -
- -
8.0 8.0 s
- - - tRSP_F -
- - - -
2.5 2.5 3.0 2.5 %
DCL DCH tTRIO tINDLYIO tOUTDLYIO tADCDIS tPORMASKHCAP
(ON)
25 54 - - - -
33 67 - - 11.5 -
40 80 100 300 15 300 ns ns s ns s
I/O Delay from Input State Change to Status Register Valid
I/O Delay from DBUS Command to I/O Output State Change Delay from I/O1 Rising Edge to ADC Value = 3F8 HCAP tPOR Mask ON (rising edge) OFF (falling edge) REGOUT tPOR Mask ON (rising edge) OFF (falling edge) Notes 9. Assured by design. 10. Assured by design. Conversion is started and completed during idle time.
(9)
2.0 1.0
5.0 3.5
9.0 8.0 s
tPORMASKHCAP
(OFF)
tPORMASKREG
OUT(ON)
2.0 1.0
5.0 3.5
9.0 8.0
tPORMASKREG
OUT(OFF)
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
Frame Threshold BUSIN
End of Initialization Command
Frame Threshold tTO
tBS
Closed BUS Switches Open
Internal Reset
Reset
Figure 4. Bus Switch and Reset Timing
9.0mA 7.0mA 1.0mA RESPONSE CURRENT tITR_R tRSP_R BUSIN 3.0V 3.0V
9.0mA 7.0mA 1.0mA tITR_F tRSP_F
Figure 5. Response Current Timing
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33784 is designed to be used with a sensor at a location remote from a centralized MCU. This device provides power, measurement, and communications between the remote sensor and the centralized MCU over a DSI 2.02 compliant bus. Sensors such as accelerometers can be powered from the regulated output of the device, and the resulting analog value from the sensor can be converted from an analog level to a digital value for transmission over the bus, in response to a query from the MCU. There are two analog inputs to a 10-bit analog-to-digital converter (ADC). Three I/O lines can be configured by the central MCU over the bus as digital inputs or digital outputs. Power is passed from BUSIN through on-chip rectifiers to an external storage capacitor. The capacitor stores energy during the highest voltage excursions of the BUSIN pin (idle) and supplies energy to power the device during low excursions of BUSIN. An under-voltage circuit provides a reset signal during lowvoltage conditions and during power-up/power-down. Data from the Central Control Unit (CCU) is applied to the BUSIN pin as voltage levels that are sensed by level detection circuitry. A serial decoder detects these transitions and decodes the incoming data. Responses are passed through a serial encoder and are transmitted via a switched current source that is slew-rate controlled.
FUNCTIONAL PIN DESCRIPTION ANALOG GROUND (AGND)
This pin is the low reference level and power return for the analog-to-digital converter (ADC). It is internally connected to RTNIN
HOLDING CAPACITOR (H_CAP)
A capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the REGOUT pin during non-idle periods.
TEST OUTPUT (TOUT)
This output is low for normal operation and will go high when the device is placed into a test mode. See Test Mode on page 14.
DBUS INPUT (BUSIN)
This pin attaches to the high side of the differential bus and responds to initialization commands.
IDDQ (IDDQ)
This input is used for measuring the quiescent current of the device during IC manufacturing test. This pin should be open in the application.
BUS RETURN IN (RTNIN)
This pin connects to the low side of the differential bus and provides the common return for power and signalling. It is internally connected to AGND.
ANALOG INPUT (AN0, AN1)
Inputs to the analog-to-digital converter.
DBUS OUTPUT (BUSOUT)
This pin is the switched BUSIN signal and is connected to the BUSIN pin of the next device in the daisy chain.
LOGIC I/O (I/O0, I/O1, I/O2)
These pins provide a logic level outputs or inputs.
BUS RETURN OUT (RTNOUT)
This pin is the switched RTNIN signal and is connected to the RTNIN pin of the next device in the daisy chain.
TEST MODE ENABLE (TEST)
A high input places this device into special test mode. See Test Mode on page 14.
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33784 - Functional Diagram Supply Voltage
Rectifier 5.0V Regulator Under-voltage Detector
Sensing & Control Receiver Control Logic Clock Analog to Digital Converter Power Stage Transmitter
Supply Voltage Sensing & Control Power Stage Bus switches
Bus Switches
Functional Internal Block Diagram
SUPPLY VOLTAGE RECTIFIER
There is an on-chip rectifier, which allows power and communications to be delivered to the 33784 over the bus. The rectifier lies between BUSIN and H_CAP. During the idle state of the bus, the rectifier allows the bus to charge an external storage capacitor attached to H_CAP. During signaling, the rectifier isolates H_CAP from the bus to prevent the bus from draining the external capacitor while signaling. The capacitor then supplies power to the 33784 during signaling. The signaling time and the size of the external capacitor must be selected so that the voltage on HCAP does not drop below 6.77V during signaling.
UNDER-VOLTAGE DETECTOR
The under-voltage detector issues a power-ON reset (POR) signal during power-up and power-down of the 33784. It also monitors the voltage on HCAP and REGOUT and issues a reset when either of these pins fall below their respective POR thresholds. The reset signal is filtered to prevent glitches on HCAP or REGOUT from causing an erroneous reset. Any time the 33784 is reset, the device will need to be re-initialized before it will respond to further commands.
LOGIC AND CONTROL RECEIVER
The receiver detects the voltage on BUSIN and senses when the bus is idle and when it is signaling. Communication on the bus always begins when the voltage on BUSIN drops below the frame threshold. This change from idle mode to signal mode is sensed by the receiver and is interpreted as the start of an incoming word. The first bit in the word begins when the bus voltage drops below the Signal threshold. This starts a counter in a serial decoder, which essentially measures the amount of time that the bus voltage is below the signal threshold. When the bus
33784
5.0V REGULATOR
An on-chip 5V regulator supplies internal power for the 33784 and also supplies power to external devices, such as accelerometers via the REGOUT pin. A bypass capacitor is required on the REGOUT pin to keep the regulator stable. All current supplied by the regulator is derived from the external capacitor attached to H_CAP.
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
voltage rises above the signal threshold, the counter measures the time the bus is above the signal threshold. When the bus voltage falls below the signal threshold again, the first bit is finished and the next bit begins. The process is repeated for each bit in the command. The decoder interprets the bit as a logic [0] if the bus spent more time below the signal threshold than above it. Conversely, the decoder interprets the bit as a logic [1] if the bus spent more time above the signal threshold than below it. The advantage to this method of communication is that it will accept data over a wide range of data rates and it is not dependent on an accurate clock. A logic [0] is typically indicated by spending 2/3 of the total bit time low, and a logic [1] is typically indicated by spending 2/3 of the total bit time high. The command ends when the bus voltage rises above the frame threshold and returns to the idle state. Each threshold comparator has hysteresis to help to filter noise on the bus during the transitions. There is also a filter, which issues a reset if the bus remains below the frame threshold for longer than the timeout limit. This allows the 33784 to reset itself if the connection to the Master IC is lost, or if power is removed from the system, or if a short-to-analog ground condition exists on one of the bus pins and the bus switch is closed.
internal operations are such that no external precision timing device is needed in the normal operation of the 33784. An LFSR-based PRBS is clocked by the oscillator and generates a random bitstream that dithers the oscillator via a switch. Dither on the clock creates a spread spectrum for noise improvement.
ANALOG-TO-DIGITAL CONVERTER
The ADC has 10-bit resolution. It uses REGOUT as a fullscale reference voltage and AGND for a zero-level reference. The ADC uses the on-chip oscillator for sequencing. The analog voltage on AN0 or AN1 is converted to a digital value in response to the Request AN0 or Request AN1 commands on the bus. Only the Request ANn commands will trigger a new conversion. The requested bits will be transmitted during the next command sent on the bus. To prevent inaccurate reporting near analog ground and the supply rail, the ADC will only report digital values between hex 0020 and 03E3. Any analog voltage that would result in a digital value below 0020 will be reported as 0020. Likewise, any voltage that would result in a value above 03E3 will be reported as 03E3. The only time the ADC will report a value outside the range of hex 0020 : 03E3 is when an error occurs during the analog conversion inside the IC. In this case, the error code 03F8 will be reported. This is summarized in Table 5, page 14. The ADC is also designed to report an error depending on the state of I/O1. If I/O1 is configured as an input and is set high when the conversion takes place, then the ADC will always report the error code 03F8. If I/O1 is low when the conversion takes place, then the ADC will report the converted digital value as described above. If I/O1 is configured as an output, then the state of I/O1 is irrelevant and the ADC will always report the converted digital value, as described above.
CONTROL LOGIC
The control logic performs the digital operations carried out by this device. Its principle functions include: * Decoding input instructions * Controlling the general purpose I /O in response to BUSIN commands * Controlling A / D conversions * Forming response words * Capturing and storing addresses * Controlling the bus switch (BS) * Resetting the device on power-up * Reading the general purpose I /O logic values and responding to requests for these values * Generating a cycle redundancy check (CRC) for the received data and transmitted data in conformance with the DBUS standard Additionally, the control logic performs error checking on the received data. If errors are found, no action is taken and no response is made. Errors include: * CRC received doesn't match CRC of received data * Number of received bits doesn't match required bit count See Figure 6 for the Control Logic Block Diagram
POWER STAGE TRANSMITTER
At the same moment the receiver detects incoming commands by sensing the voltage on the bus, the transmitter replies by changing the current flowing in the bus. Each time the bus voltage falls below the signal threshold to start a new incoming bit, the transmitter switches a fixed current source on or off. A logic [1] is indicated if the current source is switched on during the bit time. A logic [0] is indicated if the current source is switched off during the bit time. The current source is always switched off while the bus is idle. As the response current is switched on and off, the transitions are slew-rate limited to reduce EMI. Without the slew control, the fast transitions could generate higher frequency harmonics, that could interfere with receivers tuned to frequencies well above the data rate of this device.
CLOCK
An internal 10 MHz oscillator provides the clock for all logic and timing functions in the IC. The signaling system and all
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
BUS SWITCHES
A high side bus switch lies between BUSIN and BUSOUT and a low side bus switch lies between RTNIN and RTNOUT. These switches can be opened or closed via commands on the bus. The bus switch facilitates the daisy chain operation of the 33784. When the switch is open, BUSIN is isolated from BUSOUT, RTNIN is isolated from RTNOUT, and any communication that is seen on one pin will not be transmitted to the other. In this way, the CCU can initialize the first 33784 or any other slave device in the daisy chain and program an address into it. Once the first device in the daisy chain is initialized, the bus switches can be closed, effectively shorting BUSIN to BUSOUT, and RTNIN to RTNOUT. Now all communication that is seen on one pin will be passed to the other. The Master IC can send a command through the initialized device to the
next un-initialized device in the daisy chain. The process is repeated until every device in the daisy chain has been initialized with a unique address. Once a device' bus switches are closed they remain closed except for the following conditions: - reception of a CLEAR command - bus lines remain below the frame threshold for longer than the bus timeout period in which case the device will reset and the bus switches will open. - HCAP or VREG decay below the POR threshold for a time exceeding the POR Mask time in which case the device will reset and the bus switches will open. Once the bus switches open they can only be closed again with an initialization command.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES INPUT / OUTPUT PINS
There are three I/O pins on the 33784 that can serve as either logic inputs or logic outputs. At power-up or after a Clear Command, the pins default to inputs. They can be individually configured as outputs as needed via the I/O Control Command on the bus. Table 5. 10-Bit ADC Value Mapping
Hex 03FF
* * *
Table 6. 8-Bit ADC Value Mapping
Hex FA F9 F8
* * *
Description Prohibited Prohibited G Range
* * *
Description Prohibited
* * *
08 07
* * *
G Range Prohibited
* * *
03F9 03F8 03F7
* * *
Prohibited Error Code Prohibited
* * *
02 01 00
Prohibited Prohibited Prohibited
ADDRESSING
The 33784 may be connected in a daisy chain to other DBUS devices. If this device is connected in a daisy chain, then it will receive its 4-bit address during initialization on the bus.
03E4 03E3
* * *
Prohibited G Range
* * *
TEST MODE
The 33784 can be configured in a special test mode for evaluation purposes. The test mode can only be entered if all of the following conditions are true: * The TEST1 pin is at a logic high level * The correct test mode command is sent to the device on the bus * One of the internal test mode registers is accessed Accessing the test mode registers and writing different values to them can change the behavior of many of the pins on the device, including the TOUT pin, which is only active in test mode. The test mode can be intermixed with other bus commands to evaluate the behavior of internal circuit blocks. To prevent accidental activation of the test mode, the TEST1 pin should be tied externally to AGND. The TOUT pin should be grounded when not in TEST mode.
0020 001F
* * *
G Range Prohibited
* * *
0000
Prohibited
Table 6. 8-Bit ADC Value Mapping
Hex FF FE FD
* * *
Description Prohibited Error Code Prohibited
* * *
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Received Message From MASTER Data 10MHz Clock Bus Controller Frame_OK CRC Check Latch DBUS Registers INIT REQ STATUS REQ AN0 I/O CONTROL REQ ID REQ AN1 CLEAR FORMAT CONTROL TEST DATA OUT [2:0] I/O [2:0] AD_SEL AD_DATA [9:0] TEST Load Enable Data Clock Response Shifter I Response ON SEL 10MHz Clock CRC Generator Figure 6. DBUS Slave Logic Block Diagram Data Clock Command Buffer
COMMUNICATION FORMAT
DBUS messages are composed of individual words separated by a frame delay. Transfers are full duplex. Command messages from the master occur at the same time as responses from the slaves. Slave responses to commands occur during the next command message. This allows slaves
time to decode the command, retrieve the information, and prepare to send it to the master. A bus traffic example is shown in Figure 7. The example shows three commands separated by the minimum frame delay followed by a command after a longer delay.
Figure 7. Bus Traffic Example
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
In case there is a bus error (due to induced noise or a bus fault), both the master and slave devices will likely read bad data. The slave reacts to bad data by not sending a response during the next frame, and clears the any pending response. The master will detect a CRC error (if enabled) once it receives the corrupted data sent by the slave, and once again when the slave fails to respond. This is illustrated in Figure 8. CRC Error
When this error occurs, the system software needs to acknowledge this condition and resend a command of the same size so that it can receive the proper response. Failure to take corrective action will result in unintended errors as shown in Figure 8. In this case, the master will miss Responses N and N+1. CRC Error
Bus Error
Master
Command N
Command N+1
Command N+2
Command N+3
Command N+4
Slave
Response N-1
Response N CRC Error
No Response
Response N+2
Response N+3
Figure 8. Bus Traffic With Receive Error and Recovery
STANDARD DBUS COMMAND STRUCTURE
Two word sizes are available for standard DBUS commands. These are termed "long word" and "short word". A standard long word always consists of 8 data bits, 4 address bits, 4 command bits, and 4 cyclic redundancy check (CRC) bits. The data bits are always sent first, starting with the MSB, and are followed by the address bits, then the command bits, and ending with the CRC bits. Refer to Table 7, page 17. A standard short word consists of 4 address bits, 4 command bits, and 4 CRC bits. The address bits are always sent first, starting with the MSB, followed by the command bits, and ending with the CRC bits. This is also shown in Table 7. Some commands can be sent in either standard long word or standard short word format as desired. If these commands are sent in long word format, the data bits are "don't-care" for the 33784, but should all be set to 0 to maintain future compatibility. When a standard long word or short word is sent on the bus, the 33784 will calculate a CRC as each bit is received. The CRC is calculated using the polynomial X4+1 and seed 1010. The polynomial and seed cannot be changed when communicating in standard mode. At the conclusion of the transmission, the 33784 will compare the calculated CRC with the CRC included within the message. If the two match, the message is considered valid and the 33784 will act on the message accordingly. If the calculated CRC does not match the CRC included within the message, the 33784 will ignore the transmission and the message will be discarded.
ENHANCED DBUS COMMAND STRUCTURE
In addition to standard DBUS commands, the 33784 can accept enhanced DBUS commands. Like standard commands, there are two word sizes available for enhanced commands. These, like the standard long word, are termed "enhanced long word" and "enhanced short word". An enhanced long word always consists of 8 data bits, 4 address bits, 4 command bits, and 4 CRC bits. The data bits are always sent first, starting with the MSB, and are followed by the address bits, then the command bits, and ending with the CRC bits. Refer to Table 7. However, an enhanced long word differs from a standard long word in that the CRC polynomial and seed are not fixed and can be programmed into the IC via the bus. The method of programming the polynomial and seed is discussed in Format Control Command and Response, page 23. Likewise, enhanced short words will also use the polynomial and seed that have been programmed into the IC. Enhanced short words consist of 0 or 2 data bits, 4 address bits, 4 command bits, and 4 CRC bits. The data bits (if any) are sent first, followed by the address bits, followed by the command bits, and ending with the CRC bits. This is shown in Table 7. The optional data bits are only place holders and are used so that longer responses can be transmitted. If the optional data bits are used, they are "don't-care" for the 33784, but should both be set to 0 to maintain future compatibility. Some commands can be sent in either enhanced long word or enhanced short word format as desired. If these commands are sent in enhanced long word format, the data bits are "don't-care" for the 33784, but should all be set to 0 to maintain future compatibility.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
When an enhanced long word or short word is sent on the bus, the 33784 will calculate a CRC as each bit is received. The CRC is calculated using the polynomial and seed that have been programmed into the IC via the bus. At the conclusion of the transmission, the 33784 will compare the calculated CRC with the CRC included within the message. If Table 7. Standard and Enhanced DBUS Command Structure
Word Type
Standard Long Word Enhanced Long Word Standard Short Word 8-Bit Enhanced Short Word
the two match, the message is considered valid and the 33784 will act on the message accordingly. If the calculated CRC does not match the CRC included within the message, the 33784 will ignore the transmission and the message will be discarded.
Symbol First
LW ELW SW 8-Bit ESW D7 D7 D6 D6 D5 D5 D4 D4
Data
D3 D3 D2 D2 D1 D1 D0 D0 A3 A3 A3 A3 D1 D0 A3
Address
A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 C3 C3 C3 C3 C3
Command
C2 C2 C2 C2 C2 C1 C1 C1 C1 C1 C0 C0 C0 C0 C0
CRC
X3 X3 X3 X3 X3 X2 X2 X2 X2 X2 X1 X1 X1 X1 X1
Last X0 X0 X0 X0 X0
10-Bit Enhanced Short Word 10-Bit ESW
Table 8. Standard and Enhanced DBUS Response Structure
Word Type
Standard Long Word Enhanced Long Word Standard Short Word 8-Bit Enhanced Short Word
Symbol
LW ELW SW 8-Bit ESW
First D15 D15 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9
Response
D8 D8 D7 D7 D7 D7 D9 D8 D7 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D4 D4 D4 D4 D4 D3 D3 D3 D3 D3 D2 D2 D2 D2 D2 D1 D1 D1 D1 D1 D0 D0 D0 D0 D0
CRC
X3 X3 X3 X3 X3 X2 X2 X2 X2 X2 X1 X1 X1 X1 X1
Last X0 X0 X0 X0 X0
10-Bit Enhanced Short Word 10-Bit ESW
STANDARD DBUS RESPONSE STRUCTURE
There are two standard response lengths to correspond with the two standard command word lengths. A standard long response always consists of 16 data bits and 4 CRC bits. A standard short response always consists of 8 data bits and 4 CRC bits. Refer to Table 8. In both cases, the data bits are sent first, starting with the MSB, and are followed by the CRC bits. The CRC bits are calculated from the data bits using the standard polynomial X4+1 and seed 1010. The polynomial and seed cannot be changed when responding in standard mode. Normally, standard long responses will be sent for standard long commands, and standard short responses will be sent for standard short commands. However, if a long command is followed by a short command, then the response to the long command will occur during the short command and will be truncated. In this case, the response to the long command is considered invalid. Similarly, if a short command is followed by a long command, then the response to the short command will occur during the long command and will contain extra bits. In this case the response to the short command is considered invalid.
ENHANCED DBUS RESPONSE STRUCTURE
There are two enhanced response lengths to correspond with the two enhanced command word lengths. Like the standard long word, an enhanced long response always consists of 16 data bits and 4 CRC bits. The data bits are sent first, starting with the MSB, and are followed by the CRC bits. The CRC bits are calculated from the data bits using the polynomial and seed that was programmed into the IC via the bus. An enhanced short response consists of either 8 or 10 data bits and 4 CRC bits. The enhanced short response will have 8 data bits if the enhanced short command did not use the optional 2 bits, and it will have 10 data bits if the enhanced short command did use the optional 2 bits. In certain cases, the optional 2 bits might be used in the command, but due to the nature of the command, the response only contains 8 bits of data. In this circumstance, the response will be right-padded with zeros so that 10 data bits are sent, followed by the CRC. In other cases, the optional 2 bits might not be used in the command, but due to the nature of the command, the response contains 10 bits of data. In this circumstance, the 2 least significant bits of the response data will be dropped and only the 8 most significant data bits are sent, followed by the CRC. This is illustrated in logic Commands and Registers, page 18.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Normally enhanced long responses will be sent for enhanced long commands, and enhanced short responses will be sent for enhanced short commands of the same length. If an enhanced long word is sent after an enhanced short word, or an enhanced short word is sent after an
enhanced long word, or two enhanced short words of different lengths are sent in succession, then the first response will have a different length than the second command, and therefore the first response will be invalid.
LOGIC COMMANDS AND REGISTERS INTRODUCTION
The following sections describe in detail each of the commands that can be sent to the 33784. All of these commands can be sent in long-word format (standard or enhanced). Some of the commands can be sent in shortword format (standard or enhanced), but not all. Refer to the table in each section for the available formats for each command. The responses for each command can also be found in the tables. The 4-bit CRC, which is appended to every command and every response, has been omitted. Many commands have "don't-care" bits, which can be set to 0 or 1 without affecting the command. Although the 33784 will respond the same in either case, it is recommended that all "don't-care" bits be set to 0 to maintain future compatibility. will respond to other commands. The command format is found in Figure 9. The Initialization Command may be used to initialize a daisy chain device. The Initialization Command is sent to address zero. The command will be received by the next daisy chain device with its bus switch open. Reception of this command will assign the device address and close the bus switch if the BSH and BSL bits are logic [1] Once a device has received an Initialization Command, it will ignore further initialization commands unless it has received a clear command or undergone a power-ON reset. The response is sent during the next message following a valid Initialization Command to the addressed device. The response is shown in Figure 9. Because this is a long-word only command, there is no short word response. The BSH and BSL bits returned are the same as the bits sent in the command. The Request Status command can be used to find the logic commanded state of the bus switches.
INITIALIZATION COMMAND AND RESPONSE (BUSIN INPUT ONLY)
Following power-up or after a POR has occurred, the Initialization Command must be sent to the 33784 before it
Data - BSH BSL OD PA3 PA2 PA1 PA0 A3
Address A2 A1 A0 0
Command 0 0 0
Word Type LW SW & ESW (8-bit) ESW (10-bit)
Not Valid Not Valid
Response A3 A2 A1 A0 0 0 0 0 0 BSH BSL 0 PA3 PA2 PA1 PA0
Word Type LW SW & ESW (8-bit) ESW (10-bit)
No Response No Response Legend A [3:0] = Address bits. The slave address. An address value of 0000 is ignored by all devices (no initialization, no bus switch closure, and no response) BSH = High Side Bus Switch Position (1 = closed). BSL = Low Side Bus Switch Position (1 = closed). "-" = Don't care bit. Can be 0 or 1.
PA [3:0] = Bus address to set the device to. An address value of 0000 is ignored by all devices (no initialization, no bus switch closure, and no response) OD = Oscillator dither: 0 = no dither (default) 1 = dither
Figure 9. Initialization Command Response Format
REQUEST STATUS COMMAND AND RESPONSE
This command causes the addressed device to return the status of the BSH and BSL bits and the logic levels of the I / O. The command format is found in Figure 10.
The 33784 will only act on this command if the address bits in the command match the address that the device was initialized with. If the addresses do not match, the device will do nothing and no response will be generated.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
The response is sent during the next message following a valid Request Status command to the addressed device. Because this is a long-word only command, there is no shortword response.
The I/O bits reflect the logic states of the I/O pins. These states are latched into an internal register after the Request Status command is received (approximately TBD s after the bus rises above the frame threshold), and are held until the response is transmitted. Any activity that occurs on the I/O pins after the states are latched will be ignored.
Data - - - - - - - - A3
Address A2 A1 A0 0
Command 0 0 1
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
Not Valid Not Valid
Response A3 A2 A1 A0 0 0 0 0 0 BSH BSL 0 0 IO2 IO1 IO0
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
No Response No Response Legend A [3:0] = Address bits. The address of the selected device. An address value of 0000 is ignored by all devices. BSH = High Side Bus switch position (1 = closed). BSL = Low Side Bus switch position (1 = closed). "-" = Don't care bit. Can be 0 or 1. IO [2:0] = Values at logic I /Os.
Figure 10. Request Status Command and Response Format
REQUEST AN0 COMMAND AND RESPONSE
This command causes the analog voltage on the AN0 pin to be measured and converted by the on-chip 10-bit ADC. The approximate timing for the conversion following this command is shown in Figure 11. The response to this
command depends on the format in which the command was sent. The sensor data is sent in the format shown in Table 10. The 33784 will only act on this command if the address bits in the command match the address that the device was initialized with. If the addresses do not match, the device will do nothing and no response will be generated.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Frame Threshold BUSIN
End of Request ANx Command
All values are approximate and are not production tested.
13.6s
Enabled ADC Enable Disabled
4.6s
1.6s Sampling ADC Sampling Not Sampling 7.4s
4.4s ADC Conversion Completed 0.1s
Conversion Complete
Figure 11. Approximate ADC Conversion Timing
Data - - - - - - - - A3 A3 - - A3
Address A2 A2 A2 A1 A1 A1 A0 A0 A0 0 0 0
Command 0 0 0 1 1 1 0 0 0
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
Response A3 A2 A1 A0 0 0 0 0 B9 B9 B9 Legend A [3:0] = Address bits. The address of the selected device. An address value of 0000 is ignored by all devices. "-" = Don't care bit. Can be 0 or 1. B [9:0] = Measured value. B8
B7
Word Type B8 B8
B6
B7 B7
B5
B6 B6
B4
B5 B5
B3
B4 B4
B2
B3 B3 B1
B2 B2 B0
LW & ELW SW & ESW (8-bit) ESW (10-bit)
Figure 12. Request AN0 Command and Response Format
REQUEST AN1 COMMAND AND RESPONSE
This command causes the analog voltage on the AN1 pin to be measured and converted by the on-chip 10-bit ADC. The approximate timing for the conversion following this command is shown in Figure 11, page 20. The response to this command depends on the format in which the command
was sent. The sensor data is sent in the format shown in Figure 12. The 33784 will only act on this command if the address bits in the command match the address that the device was initialized with. If the addresses do not match, the device will do nothing and no response will be generated.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Data - - - - - - - - A3 A3 - - A3
Address A2 A2 A2 A1 A1 A1 A0 A0 A0 0 0 0
Command 1 1 1 0 0 0 1 1 1
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
Response A3 A2 A1 A0 0 0 0 0 B9 B9 B9 Legend A [3:0] = Address bits. The address of the selected device. An address value of 0000 is ignored by all devices. "-" = Don't care bit. Can be 0 or 1. B [9:0] = Measured value. B8
B7
Word Type B8 B8
B6
B7
B7 B5
B6
B6 B4
B5
B5 B3
B4
B4 B2
B3
B3
B2
B2
LW & ELW SW & ESW (8-bit) ESW (10-bit)
B1
B0
Figure 13. Request AN1 Command and Response Format
I / O CONTROL COMMAND AND RESPONSE
This command can be used to configure the direction of the I/O pins, and force their states if configured as outputs. Refer to Figure 14 for the command and response format. The response is sent during the next message following a valid I/O Control command to the addressed device. Because this is a long-word only command, there is no short word response. The direction (DR) bits are used to specify the direction (input or output) of each pin independently. If the DR bit for a specific I/O pin is set to 1, then that I/O pin will be an output and the state of the level (Lx) bit will determine whether the pin is driven high or low. If the DR bit for a specific I/O pin is set to 0, then that pin will be an input and the Lx bit in the command will have no affect on the state of the pin.
In the response to the I/O Control Command, the DR bits will show the direction that the pins were programmed. The Lx bits will have the values that were set in the command. These values may not reflect the actual states of the pins. To obtain the accurate states of the pins, the Request Status Command should be used. The 33784 will only act on the I/O Control Command if the address bits in the command match with the address that the device was initialized. If the addresses do not match, the device will do nothing and no response will be generated. Address `0000' is a global command. All slaves in the signal path will configure their I/O pins according to the state of the data bits. No response results from the I/O control global command.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Data -
L2 L1 L0
Address
DR2 DR1 DR0 A3 A2 A1 A0 0
Command
0 1 1
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
-
Not Valid Not Valid
Response
A3 A2 A1 A0 0 0 0 0 0 L2 L1 L0 0 DR2 DR1 DR0
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
No Response No Response Legend A [3:0] = Address bits. DR [2:0] = I / O direction bits. 1 = Output. All bits are set to 0 by reset / clear. "-" = Don't care bit. Can be 0 or 1.
L[2:0] = Level to output on I/O if configured as outputs.
Figure 14. I/O Control Command and Response Format
REQUEST ID COMMAND AND RESPONSE
This command will cause the device ID information to be read from internal storage and returned to the master. The command format is found in Figure 15. The response is sent during the next message following a valid Request ID command to the addressed device.
Because this is a long-word only command, there is no short word response. The 33784 will only act on this command if the address bits in the command match with the address that the device was initialized. If the addresses do not match, the device will do nothing and no response will be generated.
Data - - - - - - - - A3
Address A2 A1 A0 0
Command 1 0 0
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
Not Valid Not Valid
Response A3 A2 A1 A0 0 0 0 0 V3 V2 V1 V0 0 0 0 FPA R
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
No Response No Response Legend A [3:0] = Address bits. The address of the selected device. An address value of 0000 is ignored by all devices. "-" = Don't care bit. Can be 0 or 1.
V [3:0] = Device version number. The silicon version number of the device. V0 always = 0, indicating MC33784 FPAR = Some parameters in the device are trimmed by fuses. Since these parameters can be impacted by the state of the fuses a fuse parity is calculated and stored during device manufacturing. When the device is powered up the current fuse parity is checked against the stored parity. If they do not match this bit is set.
Figure 15. Request ID Command and Response Format
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
CLEAR COMMAND AND RESPONSE
This command will open the bus switch and reset all registers to the reset state. The command format is found in Figure 16. No response is generated for the clear command.
The 33784 will only act on this command if the address bits in the command match the address that the device was initialized with, or if the address bits are 0000.
Data - - - - - - - - A3 A3 - - A3
Address A2 A2 A2 A1 A1 A1 A0 A0 A0 0 0 0
Command 1 1 1 1 1 1 1 1 1
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
Response No Response No Response No Response Legend A [3:0] = Address bits. The address of the selected device. An address value of 0000 clears all devices. "-" = Don't care bit. Can be 0 or 1.
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
Figure 16. Clear Command Format and Response Format
FORMAT CONTROL COMMAND AND RESPONSE
This command allows the short-word length, the CRC polynomial, and the CRC seed to be changed. It is also the command needed to switch the device from the "standard" mode to the "enhanced" mode. The response is sent during the next message following a valid Format Control command to the addressed device. Because this is a long-word only command, there is no short word response. On power-up or following a "Clear" command, the device uses the standard DSI short-word length (8 data bits) and standard CRC polynomial (x4 + 1) and seed (1010). The registers associated with Format Control default to values that correspond to Standard DBUS operation upon power-up, or at the issuance of a "Clear" command. Changes made to the Format Control Register do not become active until the 4 bits of the format selection register are set during a single write command. It will not switch back to Standard DBUS settings unless all 4 bits of the format selection register are cleared by a single write. Any attempts to change the format will be ignored while in the enhanced mode.
The Format Control command is a long-word Command and contains 8 bits of data which are used to determine read or write, the specific format control register, and the data to be written/read. The format for this command is defined in Figure 17. If the R/W bit is set, the value in the Data Bits will be written to the format control register pointed to by the 3-bit format register address. If the R/W bit is clear, the bits in the register pointed to by the format register address will not be changed, but the values in it will be returned in the following response from the device. No data can be written to the reserved registers. The response to this command will be the data that was written/read by the command. Attempts to write to the reserved registers will return zeros in the data bits of the response. The 33784 will only act on the Format Control Command if the address bits in the command match the address that the device was initialized with. If the addresses do not match, the device will do nothing and no response will be generated. The only exception is the global address of 0000. If the address bits in the command are 0000, the 33784 will perform all normal functions associated with the command, but no response will be generated.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Data R/W ADD R2 ADD R1 ADD R0 Data 3 Data 2 Data 1 Data 0 A3
Address A2 A1 A0 1
Command 0 1 0
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
Not Valid Not Valid
Response A3 A2 A1 A0 0 0 0 0 R/W ADD R2 ADD R1 ADD R0 DAT A3 DAT A2 DAT A1 DAT A0
Word Type LW & ELW SW & ESW (8-bit) ESW (10-bit)
No Response No Response Legend A [3:0] = Address bits. The address of the selected device. R/W = Controls if this is a read or write. Write = 1. ADDR[2:0] = Pointer to Format control register which is to be accessed.
DATA[3:0] = Data to read from or write to in the pointed to Format Control Register.
Figure 17. Format Control Command and Response Format
FORMAT CONTROL REGISTERS
The enhanced DSI Register locations are shown in Figure 9. The ADDR bits in the Format Control Command select the Format Control Register to which data is written or from which data is read. The data is 4 bits. Table 9. Format Control Registers
Format Control Register Address 0 1 2 3 4 5 6 7
SEED
The Seed is the starting value loaded into the CRC checking registers before each transaction starts. The default DSI seed of 1010 would be selected by loading 1010 into control register 2. On reset or clear, the standard DSI seed is loaded into this register.
SHORT-WORD DATA LENGTH
Description CRC Polynomial Reserved Seed Reserved Reserved Short-Word Data Length Reserved Format Selection
The Short-Word Data Length controls the number of bits of data in a short word. This can be set to 8 or 10. On a reset or clear, the value in this register defaults to 8. If a number other than 8 or 10 is written to the register, it is ignored and the contents of the register are not changed. The standard DSI short-word data length would be set by loading 1000 into this register.
FORMAT SELECTION
The Format selection determines whether the standard DSI values will be used or the values in the Format register. The switch to the values in the format registers occurs when 1111 is successfully written to control register 7 in a single command. If the register is currently cleared, and one of the data bits is not received as a logic [1], the data in the register will remain all zeroes and the device will not use the Format register settings. A switch back to standard DBUS occurs when a `0000' is successfully written to control register 7. If the registers bits are all set, and one of the bits is received as a logic [1], the value of the bits in the register will remain 1111 and the switch back to Standard DSI values will not occur. This is done to reduce the possibility of switching operation modes due to a corrupted command. When using the Format Register settings, any command to change them, other than this register back to 0000, will be ignored.
CRC POLYNOMIAL
The CRC Taps control the feedback for the CRC Polynomial. The MSB represents the X3 bit. The LSB represents X0 or the value 1 if set or 0 if not set. The standard DSI CRC of X4+1 would be obtained by loading 0001 into the Format register 0. The X4 pin is always considered on, so nothing has to be done for it. On a reset or clear, the standard DSI CRC taps are loaded into these registers.
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COMMAND SUMMARY
Refer to Table 10 for a summary of the commands available in the 33784. The responses to these commands
are summarized in Table 11, page 26, and Table 12, page 27. The four-bit CRC, which appended to the end of every command and every response, has been committed.
Table 10. Command Summary
Command Names Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Description Initialization Request Status Request AN0 I /O Control Request ID Information Request AN1 Reserved Clear Reserved Reserved Format Control Reserved Reserved Reserved Reserved for test Reserved - - - D7 - - - - - - - - - - R/ W D6 BSH - - L2 - - - - - - Data (LW & ELW only) D5 BSL - - L1 - - - - - - D4 OD - - L0 - - - - - - D3 PA3 - - - - - - - - - D2 PA2 - - DR2 - - - - - - D1 PA1 - - DR1 - - - - - - D0 PA0 - - DR0 - - - - - - A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 Address A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 C3 0 0 0 0 0 0 0 0 1 1 1 Command C2 0 0 0 0 1 1 1 1 0 0 0 C1 0 0 1 1 0 0 1 1 0 0 1 C0 0 1 0 1 0 1 0 1 0 1 0
ADDR2 ADDR1 ADDR0 DATA3 DATA2 DATA1 DATA0 A3
Legend BSH = Controls closing of the High Side Bus Switch (1 = close). BSL = Controls closing of the Low Side Bus Switch (1 = close). DR [2:0] = Direction of I /O. 1 = Output. L [2:0] = Level to output on I /O if configured as outputs. "-" = Don't care bit. Can be 0 or 1. PA [3:0] = Bus Address to set the device to. R/W = Controls if this is a read or write. Write = 1. ADDR[2:0] = Pointer to Format Control Register that is to be accessed. DATA[3:0] = Data to read from or write to in the pointed to Format Control Register. OD = Oscillator dither: 0 = no dither (default) 1 = dither
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 11. Long Word Response Summary
Command Name Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Description Initialization Request Status Request AN0 I /O Control Request ID Information Request AN1 Reserved Clear Reserved Reserved Format Control Reserved Reserved Reserved Reserved for test Reserved A3 A2 A1 A0 0 0 0 0 D15 D14 D13 D12 D11 D10 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 0 0 0 0 0 0 0 0 0 0 0 0 D9 0 0 0 0 0 0 D8 0 0 0 0 0 0 D7 0 0 B9 0 V3 B9 LW & ELW D6 BSH BSH B8 L2 V2 B8 D5 BSL BSL B7 L1 V1 B7 D4 0 0 B6 L0 V0 B6 D3 PA3 0 B5 0 0 B5 D2 PA2 IO2 B4 DR2 0 B4 D1 PA1 IO1 B3 DR1 0 B3 D0 PA0 IO0 B2 DR0 FPAR B2
No Response No Response No Response No Response R/W ADDR2 ADDR1 ADDR0 DATA3 DATA2 DATA1 DATA0 No Response No Response No Response No Response No Response PA [3:0] = Bus address to set the device to. V [2:0] = Version number. R/W = Shows if last command was a read Or Write. Write = 1. ADDR[2:0] = Pointer to Format Control Register that was accessed. DATA[3:0] = Data in the pointed-to Format Control Register.
Legend A [3:0] = Address bits. The slave address. B [9:0] = Data bits. BSH = Status of the High Side Bus Switch (1 = close). BSL = Status of the Low Side Bus Switch (1 = close). DR [2:0] = I /O direction bits (1 = Output). IO [2:0] = Logic level of I /O. L [2:0] = Level to output on I /O if configured as outputs.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 12. Enhanced Short-Word Response Summary
Command Names Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Legend B [9:0] = Data bits. Description Initialization Request Status Request AN0 I /O Control Request ID Information Request AN1 Reserved Clear Reserved Reserved Format Control Reserved Reserved Reserved Reserved for test Reserved B9 B8 B7 B9 B8 B7 10-Bit ESW 8-Bit ESW No Response No Response B6 B5 B4 B3 B2 B1 B0
No Response No Response B6 B5 B4 B3 B2 B1 B0
No Response No Response No Response No Response No Response No Response No Response No Response No Response No Response No SW or ESW response except for commands 2 and 5
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EF SUFFIX (PB-FREE) 98ASB42566B ISSUE M
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 1.0 2.0 3.0
DATE 3/2008 7/2008 11/2009
DESCRIPTION OF CHANGES
* Initial Release * Added RoHS logo to page 1, provided tRSP_R temperature parameters, page 8 * Changed Part Number from PCZ33784EF/R2 to MCZ33784EF/R2 on page 1.
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MC33784 Rev 3.0 11/2009

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